1. Field of the Invention
The present invention relates to a data processing method and an apparatus having address conversion, which makes it possible to transfer data stored in a memory accessing at low speed to a memory accessing at high speed to perform high-speed accessing.
2. Description of the Related Art
Recently, there is a demand for a system, for example a printer, which performs data processing at high speed. However, since a ROM (read-only memory) for storing programs accesses data at low speed, there is such a problem that even if a central processing unit (CPU) can be used at high speed, there is a latency, thus requiring long access time. Therefore, to solve this problem, there is known a technique to realize a system in which a program is loaded to a high-speed RAM (random access memory) such as static RAM, DRAM having functions of page mode and hyperpage mode and the like, and the RAM is accessed to perform a high-speed processing. As follows is a description of the related art.
Related Art 1
In Japanese Patent Application Laid-open No. Hei 9-160824, there is disclosed a data processor which reads out program data from a read-only memory such as ROM to perform the processing. This is to transfer program data stored in a ROM generally known as low-speed access to a RAM known as high-speed access, at the time of initialization, and to access the program data normally from the RAM at high speed.
FIG. 1 is a schematic structural diagram disclosed in Japanese Patent Application Laid-open No. Hei 9-160824.
In FIG. 1, when a start signal is input to a timing generator 804 at the time of initialization, an address for accessing a low-speed ROM 806 is generated by an address generator 805, using a timing produced by the timing generator 804.
The n-bit address output from the address generator 805 is input to the ROM 806 and also a multiplexor 802, and selected as an address output from an address generator 801 normally used, by a select signal slct output from the timing generator 804, and output from the multiplexor 802.
Therefore, at the time of initialization, the address from the address generator 805 is selected as an address for RAM 803, and m-bit data read out from the ROM 806 is written in the RAM 803.
On the other hand, at the normal situation, the address from the address generator 801 is selected, and the RAM 803 outputs program data based on the address. Hence, at the time of initialization, data from the low-speed ROM 806 is transferred to the RAM 803, and at the normal situation, data is accessed from the RAM 803.
Related Art 2
A technique for selecting an area in ROM and an area in RAM is disclosed in Japanese Patent Application Laid-open No. Hei 6-223205.
FIGS. 2 and 3 are schematic structural diagrams disclosed in Japanese Patent Application Laid-open No. Hei 6-223205.
In FIG. 2, two address setup registers 901 and 902 set up an address boundary between ROM (or SRAM) and DRAM in a memory map in FIG. 3, to set up [400000H] and [B00000H] (hexadecimal notation), respectively. With two comparator circuits 903 and 904, addresses input by the address setup registers 901 and 902 and address input via an address bus are compared in size, and it is recognized by a judgement circuit 905 that memory map have been divided into three address areas as shown in FIG. 3.
With three configuration registers (CR) 906, 907 and 908, it is configured that the three addresses are either for ROM (SRAM) or for DRAM. That is to say, a bit configuration is performed such that CR906 is ROM, CR907 is DRAM, and CR908 is ROM. With the output from the judgement circuit 905 and the value configured by these three registers, a selection circuit 909 then sends the information showing which memory area is ROM, and which memory area is DRAM to a control circuit 911.
When the address is in the area of DRAM in the control circuit 911, a control signal for the DRAM is generated, and the address is divided into a column address and a row address by the multiplexor 910 and is output.
On the other hand, when the address is in the area of ROM, a control signal for the ROM is generated from the control circuit 911, and the address is output directly.
Hence, which one of ROM and DRAM is used can be freely configured only by setting up the address setup registers 901 and 902, and the configuration registers 906, 907 and 908.
Moreover, with this technique, address conversion is also possible. For example, by setting up the configuration registers 906, 907 and 908, FIG. 3A can be converted to FIG. 3B, and it looks like the address is converted.
Related Art 3
As a technique for performing the address conversion, there is known a technique disclosed in Japanese Patent Application Laid-open No. Sho 60-91460.
FIG. 4 is a schematic structural diagram disclosed in Japanese Patent Application Laid-open No. Sho 60-91460.
In FIG. 4, an address output from a central processing unit (hereinafter referred to as xe2x80x9cCPUxe2x80x9d) 1101 is transferred to an address detection circuit 1103, and when it agrees with a preset address, the agreement is informed to a gate circuit 1104.
Upon reception of the agreement information, the gate circuit 1104 opens the gate to output the data set in the offset register 1102.
The adder 1105 adds the data from the gate circuit 1104 and the address from the CPU 1101 and outputs the converted address.
When the address detection circuit 1103 judges that the address from the CPU 1101 does not agree with the preset address, the gate circuit 1104 does not open the gate and outputs xe2x80x9c0xe2x80x9d. Thus, the adder 1105 will add the address from the CPU 1101 and xe2x80x9c0xe2x80x9d, that is, the original address which has not been converted is output.
With Japanese Patent Application Laid-open No. Hei 9-160824 of the related art 1, since it is so set that read is always performed from RAM at the normal situation, the RAM capacity for storing the transferred ROM data is generally required in addition to the working RAM required for the system. Hence, it has such defects that the system cost increases, and that the ROM is required only at the time of initialization, thus it is not efficient in view of the system efficiency.
With Japanese Patent Application Laid-open No. Hei 6-223205 of the related art 2, the address for ROM (SRAM) and the multiplexed address for DRAM is changed over from the common address bus to simplify the outside circuit. To realize a high-speed access, however, recently it is normal to constitute the system such that the ROM address and the DRAM address are separately set to make it possible to access them at the same time. The related art 2 has a defect in that such a construction is not considered.
As an effect of the related art 2, the address is converted, for example, from FIG. 3A to FIG. 3B, by transferring the ROM data in the memory area from the address [000000H] to [3FFFFFH] to the DRAM area from [400000H] at the time of initialization, so that an access from the high-speed DRAM is made possible. In this case, however, the access which has directly addressed the DRAM area before the conversion becomes impossible. For example, in the case where it is programmed to write [500000H] before the conversion, it has such a problem that [500000H] after the conversion becomes ROM, thereby write of [500000H] is not possible.
With Japanese Patent Application Laid-open No. Sho 60-91460 of the related art 3, the address is monitored by the address detection circuit 1103, and when the address agrees with the predetermined address, the gate circuit 1104 is opened to add an offset value to the address. Hence, the time for agreement detection and the time for addition are required, which has a problem that a high-speed conversion is not possible.
With a view to solving the above-described problems, it is an object of the present invention to provide a data processing method and apparatus having address conversion which makes it possible to efficiently transfer data stored in a memory accessing at low speed to a memory accessing at high speed to perform high-speed accessing to the data.
Aspects of the present invention to attain the above-described object has a construction as described below.
A first aspect of the present invention is a data processing method having address conversion, which makes it possible to transfer data stored in a low-speed access memory to a high-speed access memory to perform high-speed accessing, comprising:
a memory selection step for selecting accessing to the data either from a low-speed access memory or a high-speed access memory;
a converted address decision step for deciding a converted address signal of an address signal, based on the address signal and an address conversion data set up by a central processing unit;
a comparison step for comparing the address signal and an original address in the low-speed access memory, and judging whether the address signal agrees with the original address or not; and
an address signal selection step for selecting either one signal of the address signal and the converted address signal, based on the selection result in the memory selection step and the comparison result in the comparison step,
wherein the same data can be accessed by either the low-speed access memory or the high-speed access memory.
A second aspect of the present invention is a data processing method having address conversion according to the first aspect, wherein the address signal used in the converted address decision step is characterized in that the entire bits of the signal are not set, but a plurality of predetermined bits are set.
A third aspect of the present invention is a data processing method having address conversion according to the first or second aspect, wherein the memory selection step is to select accessing, based on the capacity of a vacant area in the high-speed access memory, from the high-speed access memory if the capacity of the vacant area is sufficient for the data processing, and from the low-speed access memory if the capacity of the vacant area is not sufficient for the data processing.
A fourth aspect of the present invention is a data processing method having address conversion according to the first or second aspect, wherein the memory selection step is performed by reading a selection flag written in a nonvolatile memory.
A fifth aspect of the present invention is a data processing method having address conversion according to the third aspect, wherein the memory selection step is performed by reading a selection flag written in a nonvolatile memory.
A sixth aspect of the present invention is a data processor having address conversion, which makes it possible to transfer data stored in a low-speed access memory to a high-speed access memory to access the data at high speed, comprising:
an adder section for adding an address signal and an address conversion data set up by a central processing unit, to decide a converted address signal corresponding to the address signal;
a judgement section for judging whether the address signal agrees with an original address corresponding to the low-speed access memory which performed the data transfer; and
a selection section for selecting the converted address signal decided by the adder section, based on a detection signal output from the judgement section,
wherein the processings in the adder section and the judgement section are performed in parallel.
A seventh aspect of the present invention is a data processor having address conversion, which makes it possible to transfer data stored in a low-speed access memory to a high-speed access memory to access the data at high speed, comprising:
an adder section for adding an address signal and an address conversion data set up by a central processing unit, to decide a converted address signal corresponding to the address signal;
a judgement section for judging whether the address signal agrees with the original address corresponding to the low-speed access memory which performed the data transfer; and
a selection section for selecting a signal of either the address signal or the converted address signal, based on the detection signal output from the judgement section and a selection data showing which one of the low-speed access memory and the high-speed access memory is used for accessing the data,
wherein the processings in the adder section and the judgement section are performed in parallel.
An eighth aspect of the present invention is a data processor having address conversion according to the sixth or seventh aspect, wherein the address signal processed in the adder section is characterized in that the entire bits of the address data are not set, but a plurality of predetermined bits are set.
According to the invention of the first aspect, it is judged by the memory selection step whether the data can be processed in the high-speed access memory or not, based on the vacant area of the high-speed access memory and the like.
Moreover, to make it possible to access the converted address in the high-speed access memory based on the address signal, the converted address is first decided in the converted address decision step, based on the address signal and the address conversion data. The address signal and the original address in the low-speed access memory are then compared in the comparison step, to judge whether the address signal is the original address or not, and if there are a plurality of converted addresses, to which converted address the address signal corresponds.
If the address signal is judged to be the original address in the comparison step, and the judgement result in the memory selection step (that is, the judgement result whether the data can be accessed from the high-speed access memory) is positive, the corresponding converted address signal is selected in the address signal selection step, and the desired data is accessed from the high-speed access memory.
On the contrary, if at least one of the judgement result in the comparison step and the judgement result in the selection step is negative, not the converted address signal, but the address signal is selected in the address signal selection step, and the desired data is accessed from the original address in the low-speed access memory.
Since it can be selected, without changing the data contents in the original address, whether the data is accessed from the low-speed access memory or from the high-speed access memory, when the address conversion is not necessary, a new address conversion processing is not required, thereby contributing to the reduction of the processing time, the downsizing of the apparatus, and reduction of the program size.
According to the invention of the second aspect, as the address signal used in the converted address decision step, a plurality of predetermined bits required for the processing is used, based on the data to be transferred, hence rapid processing is performed, contributing reduction of the processing time and processing steps.
According to the third aspect of the present invention, at the time of accessing the data at high speed, accessing can be selected such that if the capacity of the high-speed access memory is not sufficient for the data processing, the data is accessed from the low-speed access memory, and if the capacity of the high-speed access memory is sufficient for the data processing, the data is accessed from the high-speed access memory. Hence, such a problem can be prevented that the system cannot operate normally by lack of the working area of the high-speed access memory.
According to the fourth and fifth aspects of the present invention, it is written in a nonvolatile memory whether the data in the low-speed access memory can be transferred to the high-speed access memory or not. Since the content in the nonvolatile memory is not erased even if the power is shut off, an user can automatically access to the high-speed access memory at the time of turning the power on or at the time of restarting, without knowing the capacity of the high-speed access memory, thereby enabling the high-speed processing.
According to the sixth aspect of the present invention, the address signal and the address conversion data are added by the adder section, to decide a converted address signal corresponding to the address signal, and in parallel, it is judged by the judgement section whether the address signal corresponds to (agrees with) the original address in the low-speed access memory which has been transferred to be processed in the high-speed access memory or not, and if there are a plurality of original addresses, which original address it is.
Then, in the selection section, the converted address signal is selected based on the detection signal output from the judgement section.
The processings in the adder section and the judgement section are performed in parallel, hence the time for deciding a desired address signal can be shortened, thereby contributing to high-speed data processing.
According to the seventh aspect of the present invention, the address signal and the address conversion data are added by the adder section, to decide a converted address signal corresponding to the address signal, and in parallel, it is judged by the judgement section whether the address signal corresponds to (agrees with) the original address in the low-speed access memory which has been transferred to be processed in the high-speed access memory or not, and if there are a plurality of original addresses, which original address it is.
If it is judged by the judgement section that the address signal is the original address, the corresponding converted address signal is selected in the selection section, to access the desired data from the high-speed access memory.
On the contrary, if it is judged by the judgement section that the address signal is not the original address, not the converted address signal, but the address signal is selected in the selection section, to access the desired data from the original address in the low-speed access memory.
Hence, such a problem can be prevented that the system cannot operate normally by lack of the working area of the high-speed access memory.
The processing in the adder section and the judgement section are performed in parallel, hence the time for deciding a desired address signal can be shortened, contributing to high-speed data processing. Moreover, it can be selected whether the data is accessed from the low-speed access memory or from the high-speed access memory, without changing the data contents in the original address. Hence, even if it is required to access the data from the low-speed access memory, complicated address processing such as reconverting the data which has been subjected to the address conversion is not required, thereby contributing reduction of the processing time, downsizing of the apparatus, and reduction of the program size.
According to the eighth aspect of the present invention, by setting a plurality of predetermined bits, not setting the entire bits of the address data, the address signal used in the adder uses the plurality of predetermined bits required for the processing, based on the data to be transferred, hence rapid processing is performed, contributing reduction of the processing time and downsizing of the apparatus.